Multiprocessors and Cache Coherence
Catagory
SISD - uniprocessor
SIMD - data-level parallelism
MISD - no commercial product
MIMD - thread-level parallelism
Shared-memory
SMP(UMA style)
NUMA
Cluster
commodity clusters
custom clusters(high end)
Cache Coherence
coherence, defines what values can be returned by a read
consistency, determines when a written value will be returned by a read
protocols
Snooping(good for UMA)
bus
scalability problem
Directory(good for NUMA)
Performance: coherence misses
Implementing Locks
atomic primitive -> lock in memory
cache coherence + atomic primitive(double check) -> lock in cache
Memory Consistency
sequential consistency
speculation
relaxed consistency
relax W→R: total store ordering (processor consistency)
relax W→W: partial store order
relax R→W and R→R: weak ordering, the PowerPC consistency model, and release consistency
Notes fo Chapter 4 of Computer Architecture: A Quantitative Approach
Multiprocessors and Cache Coherence
Added: 2012-02-13 06:18:44
From: (Joined 2011-11-05 08:09:06)
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Multiprocessors and Cache Coherence